Separate semiconductor high-voltage packaging insulation design

High-Voltage Insulation Design for Discrete Semiconductors: Keeping the Dielectric From Failing You

High voltage in discrete semiconductors is not just about peak voltage. It is about how the electric field distributes across the package, how it creeps along surfaces, and how it punches through materials that looked safe on paper. A 900-volt MOSFET in a plastic package is not the same as a 900-volt MOSFET in a ceramic package, even if the datasheet says otherwise. The insulation architecture is the difference between a device that lasts 20 years and one that arcs over after a few thousand switching cycles.

Designing insulation for high-voltage discrete packages means thinking like a high-voltage engineer, not a signal-level designer. The rules are different. The failure modes are different. And the margin for error is razor thin.

The Electric Field Is the Enemy, Not the Voltage

Why Breakdown Voltage Ratings Lie

Every datasheet lists a breakdown voltage. VDSS, VCEO, VBR. These numbers are measured under controlled lab conditions with slow ramp rates and uniform field distribution. In the real world, the electric field is never uniform. It concentrates at edges, at material interfaces, and at microscopic voids inside the mold compound.

A package rated for 1200 volts can fail at 800 volts if the field concentrates at a sharp corner inside the mold. The insulation design must manage the field gradient, not just withstand the peak voltage. This means the geometry of every internal barrier, the shape of every termination, and the smoothness of every internal surface matters as much as the bulk material properties.

The real specification target is not breakdown voltage. It is partial discharge inception voltage (PDIV). A package can withstand 1200 volts without breaking down, but if partial discharge starts at 600 volts, the insulation will erode from the inside out. Carbon tracks will grow along the discharge path, the leakage current will increase, and the device will fail catastrophically within months.

Surface Creepage vs. Bulk Insulation

Bulk insulation is the dielectric strength of the material through its thickness. Surface creepage is the distance along the surface of the package between the high-voltage terminal and any low-voltage conductor. For high-voltage discrete devices, creepage is usually the limiting factor, not bulk breakdown.

The mold compound on a TO-247 package has a bulk dielectric strength of 20 to 25 kV/mm. That sounds excellent. But the surface of the mold is rough at the microscopic level, and contaminants settle into those rough spots. The effective creepage distance along a rough surface is much shorter than the physical distance.

The specification requires a minimum creepage distance of 8 mm for 900-volt systems and 12 mm for 1200-volt systems. If the package body is too small to provide that distance, you need to add external creepage — either by potting the device in silicone gel, by using a conformal coating on the PCB, or by milling slots in the board between the high-voltage and low-voltage sections.

Internal Insulation Architecture

The Lead Frame Isolation Gap

In a standard high-voltage discrete package, the lead frame provides the electrical connection from the die to the PCB. But the lead frame also creates the insulation challenge. The drain or collector is bonded to the metal tab, and the source or emitter is bonded to the signal leads. These two conductors must be isolated inside the package.

The isolation gap between the tab and the signal leads is the critical insulation barrier. For 600-volt devices, this gap must be at least 0.5 mm wide. For 900-volt devices, it must be 1.0 mm or wider. For 1200-volt devices, 1.5 mm is the minimum.

The mold compound in this gap is under extreme electrical and mechanical stress. The CTE mismatch between the copper lead frame and the epoxy creates micro-cracks in the gap during thermal cycling. These cracks become moisture ingress paths. Moisture plus high voltage equals electrochemical migration — a slow-growing conductive filament that eventually bridges the insulation gap.

The fix is to over-mold the gap with a higher-CTE epoxy that absorbs stress, or to insert a ceramic barrier strip inside the mold. The ceramic strip does not expand or contract with temperature, so it maintains the gap width even after thousands of thermal cycles. This is standard practice for devices above 900 volts.

Die Passivation: The First Line of Defense

The silicon die itself has a thin passivation layer — usually silicon dioxide or silicon nitride — that serves as the primary insulation between the active junction and the package environment.

For high-voltage discrete devices, this passivation layer must be thick enough to block field concentration at the die edges. A standard 0.5-micrometer oxide layer is sufficient for 600 volts, but for 1200 volts, you need 1.0 to 1.5 micrometers of silicon nitride. Silicon nitride has a higher dielectric constant than oxide, which spreads the electric field more evenly across the surface.

The passivation must be pinhole-free. A single pinhole in a 1200-volt device creates a direct arc-over path. The specification requires zero pinholes per square centimeter, verified by high-potential testing at 1.5 times the rated voltage. This is not optional. This is the difference between a reliable product and a field return nightmare.

Potting and Encapsulation Strategies

For devices above 600 volts, the mold compound alone is not enough. The electric field at the surface of the package becomes too intense, and the risk of surface arcing exceeds the bulk breakdown capability.

Silicone gel potting is the standard solution for medium-voltage devices (600 to 900 volts). Silicone gel has a dielectric strength of 10 to 15 kV/mm and is self-healing — if a micro-discharge occurs, the silicone flows back into the damaged area and re-establishes the insulation barrier. The gel must be vacuum-degassed to remove air bubbles. Any bubble larger than 0.5 mm in diameter becomes a discharge site at high voltage.

For 1200 volts and above, full epoxy potting is required. Epoxy has a higher dielectric strength than silicone (15 to 25 kV/mm) and better mechanical protection. But epoxy does not self-heal. Once a discharge track forms in epoxy, it is permanent. The potting compound must be filled with thermally conductive ceramic particles to maintain thermal performance, since the potting adds thermal resistance.

The potting process must be done under vacuum. Ambient-pressure potting leaves 3 to 5 percent void content, which is unacceptable for devices above 900 volts. Vacuum potting reduces void content to below 0.5 percent.

PCB-Level Insulation Design

Creepage Slots Are Mandatory for High Voltage

The insulation does not stop at the package body. The PCB itself must provide creepage and clearance distances that match or exceed the package rating.

For 900-volt systems, IPC-2221 requires a minimum creepage of 8.0 mm and clearance of 6.0 mm. Most discrete packages have terminal pitches of 2.5 mm or less. The PCB layout must route the high-voltage trace away from low-voltage traces with enough spacing to meet these distances.

If the board is too dense to provide the required creepage, mill a slot in the PCB between the high-voltage and low-voltage sections. A 1.0 mm wide slot increases the effective creepage distance because the surface path must go around the slot. The slot must be filled with conformal coating or potting compound to prevent tracking along the slot edges.

Conformal Coating Thickness Matters

A standard acrylic conformal coating has a dielectric strength of 20 to 40 kV/mm. For 900-volt systems, a coating thickness of 50 to 75 micrometers provides a reliable surface barrier. But the coating must be continuous. Any pinhole, bubble, or thin spot becomes a discharge site.

The coating thickness must be verified by ultraviolet fluorescence inspection after application. A coating that looks uniform under visible light can have thin spots that are invisible to the naked eye but deadly at high voltage. Specify a minimum thickness of 75 micrometers for 1200-volt applications.

Silicone-based conformal coatings are better for high-voltage applications because they are more flexible and resist cracking under thermal cycling. Acrylic coatings crack easily, and cracks become tracking paths. For automotive or industrial applications where thermal cycling is severe, silicone coating is the only safe choice.

Thermal and Environmental Stress on Insulation

Moisture Is the Silent Killer

Water has a dielectric constant of 80, compared to 3 to 5 for epoxy. When moisture penetrates the mold compound, it replaces the dry epoxy in the micro-pores and dramatically increases the local capacitance. This shifts the electric field distribution and creates localized high-stress zones.

The result is partial discharge at voltages well below the rated breakdown. The discharge degrades the mold from the inside, creating carbon tracks that grow with every humidity cycle. A 900-volt device stored in a humid warehouse for six months can fail at 600 volts.

The defense is a hermetic or near-hermetic seal. For the highest reliability, use a ceramic package with a glass-to-metal seal. For plastic packages, specify a moisture sensitivity level of 1 with less than 0.1 percent moisture uptake. If the device must operate in high humidity, pot it in silicone gel. The gel blocks moisture ingress even if the mold has micro-cracks.

Thermal Cycling and Insulation Fatigue

Every thermal cycle stresses the insulation interfaces. The mold compound expands and contracts at a different rate than the die, the lead frame, and the ceramic passivation. This creates shear stress at every material boundary.

After 1000 thermal cycles from -40 to 175 degrees Celsius, the mold compound at the die edge typically develops micro-cracks 50 to 100 micrometers deep. These cracks do not cause immediate failure, but they provide a path for moisture and contaminants. Under high voltage, the contaminated crack becomes a conductive channel.

The solution is to grade the CTE of the mold compound. Use a softer, lower-modulus epoxy near the die to absorb stress, and a harder, higher-modulus epoxy near the surface to resist moisture ingress. This dual-layer mold approach reduces crack formation at the die edge by up to 60 percent compared to a single-material mold.

For ceramic-passivated devices, use a silane coupling agent on the ceramic surface before molding. The coupling agent creates a chemical bond between the ceramic and the epoxy, preventing interfacial delamination under thermal stress. Without the coupling agent, the ceramic-epoxy interface is the weak point, and it will delaminate within a few hundred cycles.

Selecting the Right Insulation Strategy

Up to 600 Volts

For standard discrete MOSFETs and diodes in this range, a high-CTI epoxy mold compound with good fill quality is sufficient. Ensure the mold has zero voids larger than 50 micrometers, use a lead frame with adequate isolation gaps, and maintain proper PCB creepage distances. No potting or special passivation is needed unless the environment is extremely harsh.

600 to 900 Volts

This is the danger zone where mold compound alone starts to fail. Use a ceramic passivation layer on the die, silicone gel potting, and a lead frame with ceramic isolation barriers. The PCB must have milled creepage slots if the layout is dense. Conformal coating on the board is mandatory.

900 Volts and Above

At this level, plastic packaging is a liability unless it is heavily potted. The preferred structure is a ceramic package with a hermetic seal, glass-to-metal terminations, and a silicon nitride passivation layer on the die. If a plastic package is unavoidable, full epoxy potting with vacuum degassing, ceramic isolation strips inside the mold, and a conformal-coated PCB with milled creepage slots are the minimum requirements. Skip any of these steps, and the field will find the weakness for you.