Method for detecting leakage current of discrete devices

Discrete Device Leakage Current Testing Methods: A Practical Guide

Leakage current is one of those parameters that quietly tells you everything about a device's health. Whether you are working with MOSFETs, Schottky diodes, or GaN HEMTs, getting the leakage number right separates a reliable design from a field return nightmare. This guide walks through the core methods engineers actually use on the bench, not just what the datasheets say.

Why Leakage Current Matters More Than You Think

Every junction in a discrete device has a tiny current that flows when it should not. That current, measured in microamps or even nanoamps, is a direct window into the integrity of the oxide layers, bond pads, and semiconductor interfaces inside the package.

A device that passes every other DC test but fails leakage is almost always carrying a latent defect. It might be a micro-crack in the passivation layer, a bond pad that got nicked during wire bonding, or a gate oxide that took a hit during ESD handling. Catching it before the device ships saves you from expensive field failures.

For input pins on ICs, the typical pass window sits between -10μA and +10μA. For power devices like Schottky diodes, the spec might be 25μA at 45V reverse bias. For GaN HEMTs under high-temperature reverse bias, you are watching the gate current drift over 30+ minutes to spot devices that will fail in the field.

Core Testing Approaches for Discrete Devices

Input Leakage: IIL and IIH on Signal Pins

The two most common leakage tests you will run on any discrete or mixed-signal device are IIL (input low leakage) and IIH (input high leakage). Here is how they work in practice.

For IIL, you power the device at VDDmax, set all non-tested pins to logic high, then force the target pin to 0V using a PMU. The current you measure flowing from VDD through that pin is your IIL value. The logic state at the pin is effectively "1" even though you are holding it at ground, which is what makes this test interesting — it reveals the resistance path from the input to the power rail.

For IIH, you do the opposite. Power at VDDmax, set non-tested pins to logic low, force the target pin to VDDmax, and measure the current flowing from that pin down to VSS. The logic state at the pin is "0" while you are holding it high.

Both tests use a source-measure unit to apply voltage and read current. The aperture time is typically set around 10ms to let the reading settle. You take multiple samples and average them. The pass criteria are compared against the datasheet limits, usually in the range of -10μA to +10μA for standard logic devices.

One thing that trips people up: if the input pin has an internal pull-up or pull-down resistor, the leakage reading will be significantly higher — sometimes tens or even hundreds of microamps. The fix is to enter a test mode that disables those resistors before measuring, or adjust your pass limits accordingly.

Quiescent Supply Current: The IDDQ Method

IDDQ testing measures the static supply current of the entire device when it is sitting in a stable state with no switching activity. The idea is simple: a device with no manufacturing defects should draw almost nothing from the supply when idle. If the current is elevated, something is wrong — a bridge, a gate oxide short, a contamination issue.

This method is especially powerful for catching defects that functional testing might miss. A device can pass every functional test and still have a leakage path that will kill it in six months. IDDQ catches that.

The test is straightforward. Apply VDDmax, let the device settle into its quiescent state, and measure the total current drawn from the supply. Compare it against the spec. For many analog and mixed-signal ICs, the IDDQ limit is in the low microamp range.

MOSFET Gate Leakage Using High-Voltage Amplifiers

Measuring gate leakage on a MOSFET is a different beast. The currents involved can be as low as 10nA or even picoamps, which means your test setup needs to be exceptionally clean.

A common approach uses a high-voltage amplifier in a feedback configuration. You set the amplifier to drive the gate to a specific voltage, and a sense resistor in the path picks up the tiny leakage current. A 10MΩ sense resistor lets you measure down to 10nA with reasonable accuracy. The amplifier itself needs ultra-low bias current — modern HV amplifiers can achieve ±2pA at 25°C, which is low enough to not swamp the measurement.

An alternative is to use a full SMU (source-measure unit) with a digital control loop. This gives you more flexibility but costs more and adds complexity. For most bench applications, the amplifier-plus-sense-resistor method hits the sweet spot of simplicity and accuracy.

Failure Analysis: When Leakage Goes Wrong

Leakage testing is not just about pass or fail. When a device fails, the leakage number itself points you toward the root cause.

Consider a real case involving a trench Schottky diode. The spec called for leakage ≤25μA at 45V reverse bias. One device in a batch came back at 150μA — six times the limit. Using emission microscopy (EMMI), the team located the hotspot. Then they ran a decap and chemical etch to expose the bond pad area. What they found: the bond process had punched through the barrier metal layer and damaged the trench structure underneath, including the gate oxide and polysilicon.

That physical damage destroyed the field-coupling effect that gives trench Schottky diodes their low leakage. The device was not electrically dead — it just leaked like a sieve.

This is why leakage testing is also an ESD damage indicator. If the input protection structures took a hit, the leakage path to VDD or VSS changes, and you see it immediately in the IIL or IIH numbers.

Stress Testing and Long-Duration Leakage Monitoring

For power devices, especially GaN HEMTs, a single snapshot of leakage is not enough. You need to watch how it changes over time under stress.

The high-temperature reverse bias (HTRB) test is the standard method. You apply VDS at 80% to 100% of the maximum rating, set VGS to the maximum gate voltage, and hold the device at temperatures above 120°C for 30 minutes or longer. You record the drain current (ID) and gate current (IG) at regular intervals.

Then you screen the data using five criteria: no data (the device burned open), IG out of limit (gate is weak), Rid out of limit (leakage is still climbing at the end of the test, meaning it will eventually fail), and Pid/Pig abnormal (the current ratios do not match the rest of the batch, indicating a latent defect).

This approach catches devices that look fine at room temperature but degrade under real operating conditions. It is slow, but it works.

Practical Tips That Save You Hours

Always do a contact test first. A bad probe touch gives you garbage leakage numbers. Use a small current to verify voltage drop across the contact — if it is too high, clean the pad or adjust the probe.

If you are testing a batch and see unstable readings, add a stress step before the leakage measurement. Apply voltage or current to the gate, drain, and source for a set time, then re-measure. This stabilizes devices that have charge trapping issues, particularly in thick wafers between 200μm and 800μm.

For devices with built-in pull resistors, do not skip the step of disabling them in test mode. The difference between a 50μA reading with the pull-up active and a 2μA reading with it disabled is the difference between a false fail and a real one.

Keep your test environment clean. Mechanical vibration and electromagnetic interference can inject noise into nanoamp-level measurements. A quiet bench and proper grounding are not optional — they are part of the test method.